1. Field of the Invention
This invention relates generally to semiconductor fabrication, and more particularly to methods of fabricating an isolation structure.
2. Description of the Related Art
The implementation of integrated circuits involves connecting isolated circuit devices through specific electrical pathways. Where integrated circuits are implemented in silicon, it is necessary, therefore, to initially isolate the various circuit devices built into the silicon substrate from one another. The circuit devices are thereafter interconnected to create specific circuit configurations through the use of global interconnect or metallization layers and local interconnect layers.
Local oxidation of silicon ("LOCOS") and trench and refill isolation represent two heavily used isolation techniques for both bipolar and metal oxide semiconductor ("MOS") circuits. In a conventional semi-recessed LOCOS process, a thin pad oxide layer is thermally grown on a silicon substrate surface and coated with a layer of chemical vapor deposition ("CVD") silicon nitride. The active regions of the substrate are then defined with a photolithographic step. The nitride layer is then dry etched and the pad oxide layer wet or dry etched with the photoresist left in place to serve as a masking layer for a subsequent channel stop implant. After the channel stop implant, field oxide regions are thermally grown by means of a wet oxidation step. The oxidation of the silicon proceeds both vertically into the substrate and laterally under the edges of the nitride layer, resulting in the formation of structures commonly known as bird's beaks.
The formation of bird's beak structures is problematic in a number of ways. To begin with, bird's beak formation can create significant limitations on the packing density of devices in an integrated circuit. Design rules for LOCOS processes must restrict the gaps between adjacent devices to account for the lateral encroachment of bird's beaks. In addition, the very shape of a bird's beak can result in the exposure of the substrate surface during subsequent overetching to open contacts for metallization. This can result in the source of the transistor becoming shorted to the well region when the metal interconnect film is deposited. This problem may be particularly acute in CMOS circuits where shallower junctions are used, due to the higher propensity for the exposure of the well regions. While some improvement in the formation of bird's beak structures has occurred as a result of the introduction of techniques such as the etchback of portions of the field oxide structures, deposition of a silicon nitride layer without a pad oxide layer, and use of a thin pad oxide covered with polysilicon, the difficulties associated with bird's beak formation have not been completely eliminated.
In the fabrication of many trench based isolation structures, a damascene process is used to pattern and etch a plurality of trenches in the silicon substrate. The trenches are then refilled with a CVD silicon dioxide or doped glass layer that is planarized back to the substrate surface using etchback planarization or chemical mechanical polishing ("CMP"). In one conventional process, a stack consisting of a sacrificial oxide layer and low pressure CVD ("LPCVD") silicon nitride layer is formed in the substrate. The stack and the underlying substrate are then etched to define the isolation trench. The trench is formed with highly sloped sidewalls which are vertically aligned with the sidewalls of the overlying nitride layer. A thermally grown liner oxide layer is next formed in the trench in anticipation of the subsequent deposition of a insulating layer which will be planarized to yield the trench isolation structure. The oxidation process to form the liner oxide consumes some of the silicon substrate, resulting in the lateral movement of the trench sidewalls. However, the sidewalls of the overlying nitride layer remain fixed since the LPCVD nitride is relatively unaffected by the oxidation process. The result is a vertical misalignment between the sidewalls of the substrate in the trench and the sidewalls of the nitride layer.
A dielectric material is next blanket deposited on the nitride layer, filling the trench. The gap between the sidewalls of the nitride layer define the initial lateral dimension of the dielectric layer and the isolation structure formed therefrom. The dielectric layer is then planarized to the nitride layer and the nitride layer is stripped to yield the completed isolation structure. As a result of the misalignment of the sidewalls of the nitride layer and the silicon sidewalls in the trench, the edges of trench isolation structure are pulled back from the silicon sidewalls, leaving only a thin and relatively short birds' beak structure covering the substrate. These areas of the substrate are vulnerable to attack by a myriad of later cleaning and etching process, such as oxide etches, HF dips and sputter cleans. The amount of pullback may be increased where the trench isolation structure is composed of a material that densifies during subsequent high temperature steps.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.